Group III-V devices, such as e.g. HEMTs, comprise a 2DEG (two dimensional Electron Gas) between two active layers, e.g. between a GaN and a AlGaN layer. It is known that this 2DEG results from spontaneous and piezo-electric polarization leading to charge separation within the materials. In most known devices of this type, the 2DEG is present at zero gate bias due to the characteristics of the materials. GaN FET devices for instance, with contacts formed on top of an AlGaN barrier layer, are normally-on devices. It is assumed that the formation of contacts on top of the epitaxial structure does not change drastically the polarization charges in a heterostructure such that if a 2DEG were present before the formation of the contacts, it would remain there after the processing. A certain negative voltage, called threshold voltage, on the gate is required to deplete the 2DEG through capacitive coupling. By applying a negative voltage to the gate an electron channel can be pinched off. This negative voltage is typically below a negative threshold voltage (Vth), typically between −2V and −8V. These transistors work in depletion-mode operation which means the channel has to be depleted to turn the transistor off.
For certain applications, such as e.g. power switching or integrated logic, negative polarity gate supply is undesired. In such a case, the gate control needs to work in such a way that, if the controlling circuitry fails for whatever reason, there is no galvanic connection between source and drain. FET devices for instance with a threshold voltage Vth>0 are normally-off devices. At zero gate voltage, so without gate control, no channel is present to conduct current. These transistors work in enhancement mode (E-mode).
To make a normally-off device, i.e. a device where no current can flow between source and drain when the gate is grounded or floating, typically a channel needs to be interrupted selectively under the gate contact (i.e. in the intrinsic part of the device, which is the part of the device where the current can be modulated) while at the same time preserving an as high as possible 2DEG density in the other regions (i.e. the extrinsic part of the device). FIG. 2 shows a cross section of a device with intrinsic and extrinsic parts. A gate bias above a certain positive threshold voltage will then induce a 2DEG under the gate contact allowing current to flow between source and drain.
Another issue with AlGaN/GaN HEMT's is the relative high contact resistance of the ohmic contacts, because of the high bandgap of the III-nitride material and the absence of impurity doping. One possible approach is the selective regrowth of n-type doped GaN, preferably with a low bandgap such as InGaN, in the regions under the ohmic contacts. In all known examples of this approach, the samples are taken out of the reactor and are patterned with SiOx for selective regrowth. This is very detrimental for the passivation of the surface of AlGaN/GaN HEMT.
Several methods have been reported to achieve such e-mode transistors:
Document U.S. 2010327293 (A1) recites an AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer that are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn-junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that the gate voltage swing can be increased.
This document does not provide a structure with good passivation
Further, growth of Junction Field Effect Transistors (JFET) where a p-type AlGaN layer on top of the AlGaN barrier causes depletion of the 2DEG, so it needs to be removed in the extrinsic device areas. The etching process to remove the p-GaN in the extrinsic device area is non-selective to the underlying layers and as such is very difficult to control.
In the above approach, p-type AlGaN is first grown everywhere on the wafer and then removed except in the gate area of the devices. As a consequence, etch depth is hard to control, plasma damage may result from it and the uncovered surface may be hard to passivate in further processing steps.
V. Kumar, et al. in “High transconductance enhancement-mode AlGaN/GaN HEMTs on SiC substrate” (see Kumar in EL39-24 2003) recite use of an inductively-coupled-plasma reactive ion etching (ICP-RIE), whereby recessed 1 μm gate-length enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs) were fabricated. These 1 μm gate-length devices exhibited maximum drain current density of 470 mA/mm, extrinsic transconductance of 248 mS/mm and threshold voltage of 75 mV. These characteristics are much higher than previously reported values for GaN-based E-mode HEMTs. However, for practical applications, the threshold voltage is too low. A unity gain cutoff frequency (fT) of 8 GHz and a maximum frequency of oscillation (fmax) of 26 GHz were also measured on these devices.
These HEMTs are grown directly onto a substrate.
W. B. Lanford, et al. in “Recessed-gate enhancement-mode GaN HEMT with high threshold voltage” (see Lanford in EL41-7 2005) recite fabrication of enhancement-mode high electron mobility transistors (E-HEMTs) on GaN/AlGaN heterostructures grown on SiC substrates. Enhancement-mode operation was achieved with high threshold voltage (VT) through the combination of low-damage and controllable dry gate-recessing and the annealing of the Ni/Au gates. As-recessed E-HEMTs with 1.0 mm gates exhibited a threshold voltage (VT) of 0.35 V, maximum drain current (ID,max) of 505 mA/mm, and maximum transconductance (gm,max) of 345 mS=mm; the corresponding post-gate anneal characteristics were 0.47 V, 455 mA/mm and 310 mS/mm, respectively. The RF performance is unaffected by the post-gate anneal process with a unity current gain cutoff frequency (fT) of 10 GHz. However, for practical applications, the threshold voltage is too low.
These HEMTs are grown directly onto a substrate.
Gate recess etching with and without post-etch RTA treatment. Due to the non-selective nature of the etch, the process is hard to control.
Yong Cai, et al. in “High-Performance Enhancement-Mode AlGaN/GaN HEMTs Using Fluoride-Based Plasma Treatment” (see Cai et al. In EDL26-7 2005) recite a novel approach in fabricating high-performance enhancement mode (E-mode) AlGaN/GaN HEMTs. The fabrication technique is based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing with an annealing temperature lower than 500° C. Starting with a conventional depletion-mode HEMT sample, they found that fluoride-based plasma treatment can effectively shift the threshold voltage from −4V to 0.9 V. Most importantly, a zero transconductance (gm) was obtained at Vgs=0V, demonstrating for the first time true E-mode operation in an AlGaN/GaN HEMT. At Vgs=0 V, the off-state drain leakage current is 28 μA/mm at a drain-source bias of 6 V. The fabricated E-mode AlGaN/GaN HEMTs with 1 μm-long gate exhibit a maximum drain current density of 310 mA/mm, a peak gm of 148 mS/mm, a current gain cutoff frequency fT of 10.1 GHz and a maximum oscillation frequency fmax of 34.3 GHz.
Herein, CF4 plasma treatment of the barrier layer is used. Fluorine plasma is known to have a detrimental effect on the dynamic behavior of the HEMT as it causes substantial increases in the dynamic on resistance. These HEMTs are directly grown on a substrate. F. Medjdoub, et al. in “Novel E-Mode GaN-on-Si MOSHEMT Using a Selective Thermal Oxidation” (and related patent application U.S. 61/080,983) recite a novel normally-off AlN/GaN metal-oxide semiconductor high electron mobility transistors (MOSHEMT) on 100-mm Si substrates for high-power applications that is demonstrated for the first time by means of a selective thermal oxidation of AlIN. The formation of a high-quality insulating AlON layer resulting from the dry thermal oxidation of AlN at 900° C. in oxygen has been identified by transmission electron microscopy and X-ray photoelectron spectroscopy. The AlN thermal oxidation appears to be highly selective toward the SiN cap layer allowing the local depletion of the 2-D electron gas (self-aligned to the gate) and thus the achievement of normally-off operation. Threshold voltage (VT) of +0.8 V and drain leakage current at VGS=0 V well below 1 μA/mm are obtained reproducibly over the wafer. The comparison of the fabricated MOSHEMTs with the control sample (identical but non-oxidized) reveals a drastic shift of VT toward positive values and three to four orders of magnitude drain leakage current reduction.
The above HEMT's comprise a gate on an insulation layer, namely on AlON.
The above document recites growth of thin barriers capped with in-situ SiN with and without thermal oxidation of the barrier. Without the thermal oxidation, due to the Schottky nature of the gate, the performance of the first approach is limited by the gate over-drive (Vg<2V). In the case of the oxidation of the Al-rich barrier, issues remain with the leakage current, dielectric breakdown and reliability of the gate oxide. In both cases, the threshold voltage is too low for practical applications.
X. Hu, et al. in “Enhancement mode AIGaN/GaN HFET with selectively grown pn junction gate” recite the fabrication and characterization of an enhancement mode AlGaInGaN heterojunction field-effect transistor (HFET) with selectively grown pn junction gate. At zero gate bias the device channel is depleted due to the high built-in potential of the gate-channel junction. The selective area growth approach enables both depletion and enhancement mode HFETs to be fabricated on the same wafer thus opening up the possibility of designing high speed, low consumption GaN-based logical integrated circuits.
In the approach by Hu et al, first a HEMT is grown, after which the wafer is taken out of the reactor to be patterned with SiOx with openings in the gate area. Subsequently, p-type AlGaN is selectively grown in the openings. However, SiOx is not a suitable passivation layer for HEMT devices and may cause the oxidation of the AlGaN barrier top surface, which leads to an increased dynamic on-resistance. Furthermore, it can only be deposited ex-situ i.e. after the wafer has been removed from the epitaxial reactor and exposed to atmosphere. After re-growth of the p-type AlGaN, the SiOx needs to be removed and replaced by a suitable passivation layer. Even further, as the AlGaN barrier has been exposed to atmospheric conditions as well as a number of processing steps, the passivation process may be difficult to control.
WO 2000/19512 A is directed to a method for forming a narrow gate of a pseudomorphic high electron mobility transistor (PHEMT). The method includes providing a structure including a III-V substrate, a channel layer over the substrate, a doped barrier layer over the channel layer, a protective layer disposed on the donor layer, an etch stop layer disposed over the protective layer, source and drain contact layers disposed over the etch stop layer, and source and drain contacts. A mask (a layer of photoresist patterned by an electron beam) is provided over the surface of the structure and includes an aperture which exposes a surface portion of the contact layers. The method as described in connection with FIGS. 3a-3e allows the formation of a gate recess by selective wet etching, thereby avoiding damage to the structure from dry etching. Further, because of the wet etching selectivity, there is a need to measure the channel current between source and drain to determine the etching point. As a consequence, the method yields greater uniformity, better reproducibility, and is less labor intense. Still, above mentioned method does not seem to enable better regrowth.